{"identifier":"nobleid:/w1/20260521/3D115D07","arkIdentifier":"ark:/48914/w1/20260521/3D115D07","version":1,"workTitle":"Conditionally robust two-pattern tests and CMOS design for testability","workType":"Journal Article","authors":"S.D. Sherlekar, Prerna Subramanian","description":null,"workUrl":null,"existingDoi":"10.1109/43.3165","createdAt":"2026-05-21T17:24:37.380370Z","canonicalUrl":"https://nobleid.org/ark:/48914/w1/20260521/3D115D07.v1"}