{"identifier":"nobleid:/w1/20260525/9A0C7076","arkIdentifier":"ark:/48914/w1/20260525/9A0C7076","version":1,"workTitle":"Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology","workType":"Journal Article","authors":"Narasimha Rao Konijeti, J. Ravindra, Pandurangaiah Yagateela","description":null,"workUrl":null,"createdAt":"2026-05-25T15:07:14.006107Z","canonicalUrl":"https://nobleid.org/ark:/48914/w1/20260525/9A0C7076.v1"}