Rapid RTL-based signal ranking for FPGA prototyping | NobleID

Main

Mint Work Search Explore Works Knowledge Graph Citation Graph Bibliometrics Receipts

v1

Rapid RTL-based signal ranking for FPGA prototyping

Identifier:nobleid.org/w1/20260515/AF40189F

Type:Journal Article

0 views

Support unavailableClaim Your Authorship

View Original Paper Source

Embeddable Badge

[![NobleID](https://www.nobleid.org/api/badge/AF40189F.svg?ark=w1%2F20260515%2FAF40189F)](https://nobleid.org/work/w1/20260515/AF40189F)

ARK Inflections

Metadata Policy

Metadata Formats

Bibliometric Analysis

Impact metrics, research fronts, co-authorship networks →

Authors & Claims

Paper Authors

Steven J. E. Wilton

Claim authorship of this work

info@nobleid.org

About FAQ Terms Policy Persistence & Resolver Service Policy